1. Field of the Invention
The present invention relates to circuits for handling data. More particularly, this invention relates to the reduction of leakage current in data handling circuits.
2. Background
Leakage current is becoming an increasingly important fraction of the total power dissipation of integrated circuits. Complementary metal-oxide semi conductor (CMOS) transistors are the current technology of choice for most data handling circuits (e.g. data processors) due to their historic advantageous characteristic of consuming power only when switching. When not switching, individual CMOS transistors consume a negligible amount of power but the leakage current for modern data processors is becoming more and more significant as component sizes shrink and transistor densities increase.
The total power consumption in a CMOS data handling circuit includes a dynamic power component, which is power consumed due to switching activity and a static power component, which arises from transistor leakage current. The leakage current is particularly significant for parts of a data handling circuit that are not doing useful work, since the leakage current quickly becomes dominant relative to the dynamic power consumption in this case.
It is known to use Multiple Threshold CMOS (MTCMOS) techniques to reduce leakage current. MTCMOS techniques allow transistors having different threshold voltages to be provided on the same chip. According to these techniques high threshold voltage transistors can be added to circuits to allow virtual power rails to be disconnected to reduce transistor leakage current. Such known techniques allow parts of the circuit to be put into a sleep mode when not in use for extended periods of time, thereby enabling leakage reduction. The state of the circuit can be retained during sleep periods by using state retention flip-flops.
However it is not only when portions of the circuit are not in use for extended periods of time that power is lost due to leakage current. In fact leakage current can be significant in circuits that are still operational, particularly in the case of applications running at low frequency or for data processors operable to run at a plurality of different frequencies. In processes where leakage current is significant, it is no longer true to assume that power consumption scales with frequency (mW/MHz). For example, a component in a 90 nanometer circuit running at 1 GHz may have 25% of its total power consumed due to leakage. If the clock frequency is reduced then leakage power can quickly become dominant so that it represents say 75% at 100 MHz and 97% at 10 MHz. Thus there is a need to reclaim the approximately linear scaling of power consumption with frequency. Recovering, to at least some extent, the linear scaling would enable data handling circuits to be run at reduced frequencies without drastic losses in efficiency.